1. Field of the Invention
The present invention relates to a MOS transistor semiconductor device, particularly to the technique of connecting dopant-diffused regions with an interconnection layer and a method of manufacturing the same.
2. Description of the Prior Art
Conventionally, the connection between the dopant-diffused regions (hereinafter referred to as "diffused layer") of such as CMOS transistors and the interconnects is carried out, as shown in the forming steps of (a)-(f) of NMOS transistor illustrated in FIGS. 3(a) to 3(j) and PMOS transistor illustrated in FIGS. 4(a) to 4(j). IN Step (a), a partial field oxide film 11, a gate oxide film 12 and a gate polysilicon layer 13 are formed on the substrate, along with a masking while patterning a resist 15 is formed. In Step (b), the PMOS regions are masked with the resist 16 and the NMOS regions are doped with phosphorus. IN Step (c), a spacer oxide film 17 is formed on a gate electrode and In the manufacturing steps of CMOS transistor, PMOS regions and NMOS regions illustrated in FIGS. 3(a)-3(j) and FIGS. 4(a)-4(j) respectively, are treated simultaneously. IN Step (d), an oxide film 30 is formed. In Step (e), the PMOS regions are masked with the resist 161 and the NMOS regions are doped with arsenic to form N-type dopant regions. In Step (f), the NMOS regions are masked with resist 162 and,the PMOS regions are doped with boron to form P-type dopant regions. In Step (g), a BPSG film is deposited. In Step (h), in order to make the BPSG film as an interlayer-insulating film 2, a reflow process is carried out with a high temperature treatment, so that a surface is flattened. Subsequently, in Step (i), the interlayer-insulating film 2 deposited on the diffused layers 1 and a metal interconnect material 3 are etched. The etching is made to go to the upper surfaces of the diffused layers which open to the substrate, thus forming connection holes 4. To ensure that the connection holes 4 are located within the openings in the diffused layers 1, the size D of each opening in the diffused layers is set larger than the diameter d of each connection hole 4. The spaces between them are known as alignment margins 5. In this way, both are connected.
Accordingly, the alignment margins make the diffused regions have excessive area. As a result, the area occupied by MOS transistors on a silicon substrate surface increases. This presents a problem in packing semiconductor devices at a higher density.
In view of the foregoing situations, it is an object of the present invention to provide a MOS transistor semiconductor device which reduces the area on the surface of the silicon substrate occupied by diffused layers, permits semiconductor devices to be packed at a higher density, and suppresses the resistances of interconnects. Also, it is another object of the invention to provide a method of manufacturing such a MOS transistor semiconductor device.